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FEATURES ADOPTTM Optimal Positioning Technology for Superior Load Transient Response and Fewest Output Capacitors Complies with VRM 9.0 and Intel VR Down Guideline with Lowest System Cost Digitally Selectable 2- or 3-Phase Operation at up to 500 kHz per Phase Quad Logic-level PWM Outputs for Interface to External High-Power Drivers Active Current Balancing between All Output Phases Accurate Multiple VRM Module Current Sharing 5-Bit Digitally Programmable 1.1 V to 1.85 V Output Total Output Accuracy 0.8% Over Temperature Current-Mode Operation Short Circuit Protection Enhanced Power Good Output Detects Open Outputs in Multi-VRM Power Systems Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components APPLICATIONS Desktop PC Power Supplies for: Intel Pentium(R) 4 Processors AMD Athlon Processors VRM Modules
5-Bit Programmable 2-/3-Phase Synchronous Buck Controller ADP3163
FUNCTIONAL BLOCK DIAGRAM
VCC PC
ADP3163
UVLO & BIAS SET RESET CROWBAR REF GND 3.0V REFERENCE DAC+20% 2-/3-PHASE DRIVER LOGIC PWM1 PWM2 PWM3
PGND
CT
OSCILLATOR POWER GOOD PWRGD
SHARE CMP DAC+20% CS- CMP CS+ FB COMP SOFT START gm VID DAC
VID4 VID3 VID2 VID1 VID0
GENERAL DESCRIPTION
The ADP3163 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high performance Intel processors. The ADP3163 uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.1 V and 1.85 V. The ADP3163 uses a current mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. These stages share the dc output current to reduce overall output voltage ripple. An active current balancing function ensures that all phases carry equal portions of the total load current, even under large transient loads, to minimize the size of the inductors.
The ADP3163 also uses a unique supplemental regulation technique called active voltage positioning (ADOPT) to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3163 also provides accurate and reliable short circuit protection, adjustable current limiting, and an enhanced Power Good output that can detect open outputs in any phase for single or multi-VRM systems. The ADP3163 is specified over the commercial temperature range of 0C to 70C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc. Pentium is a registered trademark of Intel Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADP3163-SPECIFICATIONS1 (VCC = 12 V, I
Parameter FEEDBACK INPUT Accuracy 1.1 V Output 1.6 V Output 1.85 V Output Line Regulation Input Bias Current Crowbar Trip Point Crowbar Reset Point Crowbar Response Time REFERENCE Output Voltage Output Current VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage OSCILLATOR Maximum Frequency2 Frequency Variation Symbol VFB Conditions
REF
= 150 A, TA = 0 C to 70 C, unless otherwise noted.)
Min Typ Max Unit
VFB IFB VCROWBAR tCROWBAR VREF IREF VIL(VID) VIH(VID) IVID RVID
1.091 1.587 1.835 VCC = 10 V to 14 V % of Nominal Output % of Nominal Output Overvoltage to PWM Going Low 115 40
1.1 1.6 1.85 0.01 5 120 50 400 3.00
1.109 1.613 1.865 50 125 60
V V V % nA % % ns V A V V A k V kHz kHz kHz kHz A A M mmho A V mV kHz mV mV mV A ns
2.952 300
3.048
0.8 2.0 VID(X) = 0 V 33 2.7 3000 475 850 1100 260 40 70 43 3.0 90 3.3
fCT(MAX) fCT ICT
CT Charge Current ERROR AMPLIFIER Output Resistance Transconductance Output Current Maximum Output Voltage Output Disable Threshold -3 dB Bandwidth CURRENT SENSE Threshold Voltage
TA = 25C, CT = 150 pF TA = 25C, CT = 68 pF TA = 25C, CT = 47 pF TA = 25C, VFB in Regulation TA = 25C, VFB = 0 V
575 1000 1300 300 65 1 2.2 575 3.0 800 500 158 92 0 1 50
675 1250 1500 340 80
RO(ERR) gm(ERR) IO(ERR) VCOMP(MAX) VCOMP(OFF) BWERR VCS(TH)
2.0 FB Forced to 0 V FB Forced to VOUT - 3% COMP = Open CS+ = VCC, FB Forced to VOUT - 3% FB 750 mV 0.8 V SHARE 1 V CS+ = CS- = VCC CS+ - (CS-) 173 mV 143 80
2.45
875
173 108 5 5
Input Bias Current Response Time to PWM Going Low CURRENT SHARING Output Source Current Output Sink Current Maximum Output Voltage PHASE CONTROL Input Low Voltage Input High Voltage POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Voltage Low Response Time
ICS+, ICS- tCS
2 VSHARE(MAX) VIL(PC) VIH(PC) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Percent of Nominal Output Percent of Nominal Output IPWRGD(SINK) = 1 mA FB Forced to VOUT - 3% 300 3.0 400
mA A V V V % % mV ns
0.8 2.0 75 115 80 120 375 250 85 125 525
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Parameter PWM OUTPUTS Output Voltage Low Output Voltage High Duty Cycle Limit Per Phase2 SUPPLY DC Supply Current Normal Mode No CPU Mode UVLO Mode UVLO Threshold Voltage UVLO Hysteresis Symbol VOL(PWM) VOH(PWM) DC Conditions IPWM(SINK) = 400 A IPWM(SOURCE) =400 A PC = GND PC = REF Min Typ 100 5.0 Max 500 50 33 Unit mV V % %
4.0
ICC ICC(NO CPU) ICC(UVLO) VUVLO
VID4 - VID0 = Open VCC VUVLO, VCC Rising 5.9 0.5
3.75 3.5 350 6.4 0.8
5.5 5.5 500 6.9 1.0
mA mA A V V
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Guaranteed by design, not tested in production. Specifications subject to change without notice.
PIN CONFIGURATION RU-20
VID4 1 VID3 2 VID2 3 VID1 4 VID0 5 SHARE 6 COMP 7 GND 8 FB 9 CT 10 20 VCC 19 REF 18 PWM1
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +15 V CS+, CS- . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC +0.3 V All Other Inputs and Outputs . . . . . . . . . . . . -0.3 V to +10 V Operating Ambient Temperature Range . . . . . . . 0C to 70C Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND.
ADP3163
TOP VIEW (NOT TO SCALE)
17 PWM2 16 PWM3 15 PC 14 PGND 13 CS- 12 CS+ 11 PWRGD
ORDERING GUIDE
Model
ADP3163JRU
Temperature Range
0C to 70C
Package Description
Thin Shrink Small Outline
Package Option
RU-20 (TSSOP-20)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3163 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS
Pin 1-5
Name VID4 - VID0 SHARE
Function Voltage Identification DAC Inputs. These pins are pulled up to an internal 3 V reference, providing a Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.1 V to 1.85 V. Leaving all five DAC inputs open results in the ADP3163 going into a "No CPU" mode, shutting off its PWM outputs. Current Sharing Output. This pin is connected to the SHARE pins of other ADP3163s in multiple VRM systems to ensure proper current sharing between the converters. The voltage at this output programs the output current control level between CS+ and CS-. Error Amplifier Output and Compensation Point. Ground. FB, REF and the VID DAC of the ADP3163 are referenced to this ground. This is a low current ground that can also be used as a return for the FB pin in remote voltage sensing applications. Feedback Input. Error amplifier input for remote sensing of the output voltage. External capacitor CT connection to ground sets the frequency of the device. Open drain output that signals when the output voltage is outside of the proper operating range or when a phase is not supplying current even if the output voltage is in specification. Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS-. Current Sense Negative Node. Negative input for the current comparator. Power Ground. All internal biasing and logic output signals of the ADP3163 are referenced to this ground. Phase Control Input. This logic-level input determines the number of active phases and the duty cycle limit of each phase. Logic-Level Output for the Phase 3 Driver. Logic-Level Output for the Phase 2 Driver. Logic-Level Output for the Phase 1 Driver. 3.0 V Reference Output. Supply Voltage for the ADP3163.
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20
COMP GND FB CT PWRGD CS+ CS- PGND PC PWM3 PWM2 PWM1 REF VCC
ADP3163
1 VID4 2 VID3 5-BIT CODE 3 VID2 4 VID1 5 VID0 6 SHARE 7 COMP 100 100nF 10 CT PWRGD 11 8 GND 9 FB VCC 20 REF 19 PWM1 18 PWM2 17 PWM3 16 PC 15 PGND 14 CS- 13 CS+ 12 20k 1F 100nF 12V
Table I. PWM Outputs vs. Phase Control Code
PC REF GND
PWM3 ON OFF
PWM2 ON ON
PWM1 ON ON
Maximum Duty Cycle 33% 50%
VFB
AD820
1.2V
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
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Typical Performance Characteristics-ADP3163
10
4.5
4.4
SUPPLY CURRENT - mA
FREQUENCY - MHz
4.3
1.0
4.2
4.1
0.1 0 50 150 200 100 CT CAPACITANCE - pF 250 300
4.0 0 500 1500 2000 1000 OSCILLATOR FREQUENCY - kHz 2500 3000
TPC 1. Oscillator Frequency vs. Timing Capacitor (CT)
TPC 2. Supply Current vs. Oscillator Frequency
25 TA = 25 C VOUT = 1.6V 20
NUMBER OF PARTS - %
15
10
5
0 -0.5
0 OUTPUT ACCURACY - % of Nominal
0.5
TPC 3. Output Accuracy Distribution
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Table II. Output Voltage vs. VID Code
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT(NOM) No CPU 1.100 V 1.125 V 1.150 V 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V 1.425 V 1.450 V 1.475 V 1.500 V 1.525 V 1.550 V 1.575 V 1.600 V 1.625 V 1.650 V 1.675 V 1.700 V 1.725 V 1.750 V 1.775 V 1.800 V 1.825 V 1.850 V
phase is inherently limited to 50% for 2-phase operation and 33% for 3-phase operation. While one phase is on, all other phases remain off. In no case can more than one output be high at any time.
Output Voltage Sensing
The output voltage is sensed at the FB pin allowing for remote sensing. To maintain the accuracy of the remote sensing, the GND pin should also be connected close to the load. A voltage error amplifier (gm) amplifies the difference between the output voltage and a programmable reference voltage. The reference voltage is programmed between 1.1 V and 1.85 V by an internal 5-bit DAC, which reads the code at the voltage identification (VID) pins. (Refer to Table II for the output voltage versus VID pin code information.)
Active Voltage Positioning
The ADP3163 uses Analog Devices Optimal Positioning Technology (ADOPT), a unique supplemental regulation technique that uses active voltage positioning and provides optimal compensation for load transients. When implemented, ADOPT adjusts the output voltage as a function of the load current, so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning has poor dynamic performance, rendering it ineffective under the stringent repetitive transient conditions required by high performance processors. ADOPT, however, provides optimal bandwidth for transient response that yields optimal load transient response with the minimum number of output capacitors.
Reference Output
THEORY OF OPERATION
A 3.0 V reference is available on the ADP3163. This reference is normally used to set the voltage positioning accurately using a resistor divider to the COMP pin. In addition, the reference can be used for other functions such as generating a regulated voltage with an external amplifier. The reference is bypassed with a 1 nF capacitor to ground. It is not intended to supply large capacitive loads, and it should not be used to provide more than 300 A of output current.
Cycle-by-Cycle Operation
The ADP3163 combines a current-mode, fixed frequency PWM controller with multiphase logic outputs for use in a 2- or 3-phase synchronous buck power converter. Multiphase operation is important for switching the high currents required by high performance microprocessors. Handling the high current in a single-phase converter would place unreasonable requirements on the power components such as inductor wire size and MOSFET ON-resistance and thermal dissipation. The ADP3163's high-side current sensing topology ensures that the load currents are balanced in each phase, such that no single phase has to carry more than it's share of the power. An additional benefit of high side current sensing over output current sensing is that the average current through the sense resistor is reduced by the duty cycle of the converter allowing the use of a lower power, lower cost resistor. The outputs of the ADP3163 are logic drivers only and are not intended to directly drive external power MOSFETs. Instead, the ADP3163 should be paired with drivers such as the ADP3413 or ADP3414. The frequency of the ADP3163 is set by an external capacitor connected to the CT pin. The phase relationship and number of active output phases is determined by the state of the phase control (PC) pin as shown in Table I. The error amplifier and current sense comparator control the duty cycle of the PWM outputs to maintain regulation. The maximum duty cycle per
During normal operation (when the output voltage is regulated), the voltage-error amplifier and the current comparator are the main control elements. The voltage at the CT pin of the oscillator ramps between 0 V and 3 V. When that voltage reaches 3 V, the oscillator sets the driver logic, which sets PWM1 high. During the ON time of Phase 1, the driver IC turns on the Phase 1 high-side MOSFET. The CS+ and CS- pins monitor the current through the sense resistor that feeds all the high side MOSFETs. When the voltage between the two pins exceeds the threshold level, the driver logic is reset and the PWM1 output goes low. This signals the driver IC to turn off the Phase 1 high side MOSFET and turn on the Phase 1 low side MOSFET. On the next cycle of the oscillator, the driver logic toggles and sets PWM2 high. On each following cycle of the oscillator, the driver logic cycles between each of the active PWM outputs based on the logic state of the PC pin. In each case, the current comparator resets the PWM output low when its threshold is reached. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the gm amplifier, which in turn leads to an increase in the current comparator threshold, thus programming more load current to be delivered so that voltage regulation is maintained.
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Active Current Sharing
The ADP3163 ensures current balance in all the active phases by sensing the current through a single sense resistor. During one phase's ON time, the current through the respective high side MOSFET and inductor is measured through the sense resistor. When the comparator threshold is reached, the high side MOSFET turns off. On the next cycle the ADP3163 switches to the next phase. The current is measured with the same sense resistor and the same internal comparator, ensuring accurate matching. This scheme is immune to imbalances in the MOSFET's RDS(ON) and inductor parasitic resistance. If for some reason one of the phases fails, the other phases will still be limited to their maximum output current (one over the total number phases times the total short circuit current limit). If this is not sufficient to supply the load, the output voltage will droop and cause the PWRGD output to signal that the output voltage has fallen out of its specified range. If one of the phases has an open circuit failure, the ADP3163 will detect the open phase and signal the problem via the PWRGD pin (see Power Good Monitoring section).
Current Sharing in Multi-VRM Applications
voltage specification even when one VRM is not functioning. The ADP3163 addresses this problem by monitoring both the output voltage and the switch current to determine the state of the PWRGD output. The output voltage portion of the Power Good monitor dominates; as long as the output voltage is outside the specified window, PWRGD will remain low. If the output voltage is within specification, a second circuit checks to make sure that current is being delivered to the output by each phase. If no current is detected in a phase for three consecutive cycles, it is assumed that an open circuit exists somewhere in the power path, and PWRGD will be pulled low.
Output Crowbar
The ADP3163 includes a SHARE pin to allow multiple VRMs to accurately share load current. In multiple VRM applications, the SHARE pins should be connected together. This pin is a low impedance buffered output of the COMP pin voltage. The output of the buffer is internally connected to set the threshold of the current sense comparator. The buffer has a 400 A sink current, and a 2 mA sourcing capability. The strong pull-up allows one VRM to control the current threshold set point for all ADP3163s connected together. The ADP3163's high accuracy current set threshold ensures good current balance between VRMs. Also, the low impedance of the buffer minimizes noise pick up on this trace which is routed to multiple VRMs. This circuit operates in addition to the active current sharing between phases of each VRM described above.
Short Circuit Protection
The ADP3163 includes a crowbar comparator that senses when the output voltage rises higher than the specified trip threshold, VCROWBAR. This comparator overrides the control loop and sets both PWM outputs low. The driver ICs turn off the high side MOSFETs and turn on the low side MOSFETs, thus pulling the output down as the reversed current builds up in the inductors. If the output overvoltage is due to a short of the high side MOSFET, this action will current limit the input supply or blow its fuse, protecting the microprocessor from destruction. The crowbar comparator releases when the output drops below the specified reset threshold, and the controller returns to normal operation if the cause of the over voltage failure does not persist.
Output Disable
The ADP3163 includes an output disable function that turns off the control loop to bring the output voltage to 0 V. Because an extra pin is not available, the disable feature is accomplished by pulling the COMP pin to ground. When the COMP pin drops below 0.8 V, the oscillator stops and all PWM signals are driven low. When in this state, the reference voltage is still available. The COMP pin should be pulled down with an open drain structure capable of sinking at least 2 mA.
APPLICATION INFORMATION
The ADP3163 has multiple levels of short circuit protection to ensure fail-safe operation. The sense resistor and the maximum current sense threshold voltage given in the specifications set the peak current limit. When the load current exceeds the current limit, the excess current discharges the output capacitor. When the output voltage is below the foldback threshold, VFB(LOW), the maximum deliverable output current is cut by reducing the current sense threshold from the current limit threshold, VCS(CL), to the foldback threshold, VCS(FOLD). Along with the resulting current foldback, the oscillator frequency is reduced by a factor of five when the output is 0 V. This further reduces the average current in short circuit.
Power Good Monitoring
The design parameters for a typical Intel Pentium 4 CPU application are as follows: Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.5 V Nominal output voltage at no load (VONL) = 1.475 V Nominal output voltage at 65 A load (VOFL) = 1.377 V Static output voltage drop based on a 1.5 m load line (ROUT) from no load to full load (V) = VONL - VOFL = 1.475 V - 1.377 V = 98 mV Maximum Output Current (IO) = 65 A Number of Phases (n) = 3
CT Selection--Choosing the Clock Frequency
The Power Good comparator monitors the output voltage of the supply via the FB pin. The PWRGD pin is an open drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the specified range of the nominal output voltage requested by the VID DAC. PWRGD will go low if the output is outside this range. Short circuits in a VRM power path are relatively easy to detect in applications where multiple VRMs are connected to a common power plane. VRM power train open failures are not as easily spotted, since the other VRMs may be able to supply enough total current to keep the output voltage within the Power Good REV. 0
The ADP3163 uses a fixed-frequency control architecture. The frequency is set by an external timing capacitor, CT. The clock frequency and the state of the PC pin determine the switching frequency, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. With PC tied to REF, a clock frequency of 600 kHz sets the switching frequency of each phase, fSW, to 200 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. To achieve a 600 kHz oscillator frequency, the required timing capacitor value is 150 pF. For good frequency stability and initial accuracy, it is recommended to use a capacitor with low temperature coefficient and tight -7-
ADP3163
tolerance, e.g., an MLC capacitor with NPO dielectric and with 5% or less tolerance.
Inductance Selection
The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs, but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. In a three-phase converter, a practical value for the peak-to-peak inductor ripple current is under 50% of the dc current in the same inductor. A choice of 50% for this particular design example yields a total peak-to-peak output ripple current of 12% of the total dc output current. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor and input and output voltages. L= (VIN - VOUT ) x VOUT VIN x fSW x IL ( RIPPLE ) (1)
the circuitry surrounding the inductor. Closed-loop types, such as pot cores, PQ, U, and E cores, or toroids, cost more, but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor. Table III gives some examples.
Table III. Magnetics Design References
Magnetic Designer Software Intusoft (http://www.intusoft.com) Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-08
Selecting a Standard Inductor
The companies listed in Table IV can provide design consultation and deliver power inductors optimized for high power applications upon request.
Table IV. Power Inductor Manufacturers
For an 11 A peak-to-peak ripple current, which corresponds to 50% of the 22 A full-load dc current in an inductor, Equation 1 yields an inductance of: L= (12 V - 1.5 V ) x 1.5 V = 596 nH 600 kHz 12 V x x 11 A 3
Coilcraft (847)639-6400 http://www.coilcraft.com Coiltronics (561)752-5000 http://www.coiltronics.com Sumida Electric Company (408)982-9660 http://www.sumida.com
RSENSE
A 600 nH inductor can be used, which gives a calculated ripple current of 10.9 A at no load. The inductor should not saturate at the peak current of 27 A, and should be able to handle the sum of the power dissipation caused by the average current of 22 A in the winding and the core loss. The output ripple current is smaller than the inductor ripple current due to the three phases partially canceling. This can be calculated as follows:
The value of RSENSE is based on the maximum required output current. The current comparator of the ADP3163 has a minimum current limit threshold of 143 mV. Note that the 143 mV value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and tolerances. The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO, which equals the peak inductor current value less half of the peak-to-peak inductor ripple current. From this, the maximum value of RSENSE is calculated as:
RSENSE VCSCL ( MIN ) 143 mV = = 5.3 m 65 A 10.9 A IO I L ( RIPPLE ) + + 3 2 n 2
IO
n x VOUT x (VIN - n x VOUT ) VIN x L x fOSC 3 x 1.5 V x (12 V - 3 x 1.5 V ) = = 7.81 A 12 V x 600 nH x 600 kHz IO =
(2)
Designing an Inductor
(3)
Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-M(R) from Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. Two main core types can be used in this application. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in -8-
In this case, 5 m was chosen as the closest standard value. Once RSENSE has been chosen, the output current at the point where current limit is reached, IOUT(CL), can be calculated using the maximum current sense threshold of 173 mV:
IOUT ( CL ) = n x IOUT ( CL )
VCSCL ( MAX ) n x I L ( RIPPLE ) - RSENSE 2 173 mV 3 x 10.9 A = 3x - = 87.5 A 5 m 2
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L1 1H VIN12V + VINRTN 10 F 2 MLCC R4 10 D1 MBR052LTI Q1 FZ649TA 1 BST 2 IN SW 7 PGND 6 DRVL 5 Q7 FDB8030L 3 NC C6 15nF Z1 ZMM5263BCT 4 VCC C12 4.7 F DRVH 8 C4 4.7 F R5 20 Q3 FDB7030L R6 2k C1 C2 C3 R7 5m + + 270 F/16V x 3 OS-CON SP SERIES 18m ESR(EACH)
U2 100nF ADP3414
C11
2200 F/6.3V 9 L2 RUBYCON MBZ SERIES 600nH 13m ESR (EACH) C13 15nF R8 2 + +
VCC(CORE) 1.1V - 1.85V
U1 ADP3163
1 VID4 C7 1nF D2 MBR052LTI 2 VID3 REF 19 PWM1 18 1 BST 4 VID1 PWM2 17 PWM3 16 PC 15 PGND PGND 14 CS- 13 CS+ 12 PWRGD 11 D3 MBR052LTI 5 VID0 6 SHARE 7 COMP RB 10.0k 8 GND 9 FB 10 CT C9 150pF 2 IN 3 NC 4 VCC C15 4.7 F FROM CPU 3 VID2 VCC VCC 20
C20
C29
65A VCC(CORE)RTN
U3 100nF ADP3414
C14 Q4 FDB7030L DRVH DRVH 8 SW SW 7 PGND 6 DRVL DRVL 5 Q8 FDB8030L L3 600nH C16 15nF R9 2
10 F 27 MLCC
Figure 2. 65A Intel Pentium 4CPU Supply Circuit, VR Down Guideline Design
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R3 1k C18 4.7 F C10 100pF
RA 32.4k Q1 2N7000
OUTEN
U5 10k 1/6 7404
R2
COC 1.2nF
U4 100nF ADP3414
1 BST 2 IN 3 NC 4 VCC
C17 Q5 FDB7030L DRVH DRVH 8 SW SW 7 PGND 6 DRVL DRVL 5 Q9 FDB8030L L4 600nH C19 15nF R10 2
ADP3163
ADP3163
At output voltages below 750 mV, the current sense threshold is reduced to 108 mV, and the ripple current is negligible. Therefore, at dead short the output current is reduced to: VCS ( SC ) 108 mV = 3x = 65 A (5) RSENSE 5 m To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least: IOUT ( SC ) = n x
PRSENSE = I SENSE ( RMS ) x RSENSE
2
VGNL = VGNL 0 + n x t D x RSENSE VGNL = 1V +
I L ( RIPPLE ) x RSENSE x nI VIN - VOUT - x L 2 x nI
10.9 A x 5 m x 12.5 12 V - 1.5 V - x 2 600 nH 2 x 60 ns x 5 m x 12.5 = 1.144 V
(10)
(6) The divider resistors (RA for the upper and RB for the lower) can now be calculated, assuming that the internal resistance of the gm amplifier (ROGM) is 1 M:
RB = VREF VREF - VGNL - gm x (VONL - VVID ) RT 3V = 8.59 k 3 V - 1.144 V - 2.2 mmho x (1.475 V - 1.5 V ) 6.31 k
where:
IO V x OUT (7) n x VIN In this formula, n is the number of phases, and is the converter efficiency, in this case assumed to be 85%. Combining Equations 6 and 7 yields: ISENSE ( RMS ) =
2 2
PRSENSE =
65 A 1.5 V x x 5 m = 1.0 W 3 0.85 x 12 V
2
RB =
(11)
Output Resistance
This design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc output resistance of:
Choosing the nearest 1% resistor value gives RB = 8.66 k. Finally, RA is calculated:
RA = 1 1 = = 23.8 k 1 1 1 1 1 1 (12) - - - - RT ROGM RB 6.31 k 1 M 8.66 k
ROUT =
VONL - VOFL 1.475 V - 1.377 V = = 1.5 m IO 65 A
(8)
Choosing the nearest 1% resistor value gives RA = 23.7 k.
COUT Selection
The required dc output resistance can be achieved by terminating the gm amplifier with a resistor. The value of the total termination resistance that will yield the correct dc output resistance:
RT = nI x RSENSE 12.5 x 5 m = = 6.31 k n x gm x ROUT 3 x 2.2 mmho x 1.5 m
(9)
where nI is the division ratio from the output voltage signal of the gm amplifier to the PWM comparator CMP1, gm is the transconductance of the gm amplifier itself, and n is the number of phases.
Output Offset
The required equivalent series resistance (ESR) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be less than or equal to the specified output resistance (ROUT), in this case 1.5 m. The capacitance must be large enough that the voltage across the capacitors, which is the sum of the resistive and capacitive voltage deviations, does not deviate beyond the initial resistive step while the inductor current ramps up or down to the value corresponding to the new load current. One can, for example, use nine MBZ-type capacitors from Rubycon, with 2200 F capacitance, a 6.3 V voltage rating, and 13 m ESR. The nine capacitors have a maximum total ESR of 1.44 m when connected in parallel. As long as the capacitance of the output capacitor bank is above a critical value and the regulating loop is compensated with Analog Devices' proprietary compensation technique (ADOPT), the actual capacitance value has no influence on the peak-topeak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows:
COUT ( CRIT ) = IO L x= ROUT x VOUT n 65 A 600 nH x = 5.78 mF 1.5 m x 1.5 V 3
Intel's specification requires that at no load the nominal output voltage of the regulator be offset to a lower value than the nominal voltage corresponding to the VID code. The offset is introduced by realizing the total termination resistance of the gm amplifier with a divider connected between the REF pin and ground. The resistive divider introduces an offset to the output of the gm amplifier that, when reflected back through the gain of the gm stage, accurately positions the output voltage near its allowed maximum at light load. Furthermore, the output of the gm amplifier sets the current sense threshold voltage. At no load, the current sense threshold is increased by the peak of the ripple current in the inductor and reduced by the delay between sensing when the current threshold has been reached and when the high side MOSFET actually turns off. These two factors are combined with the inherent voltage (VGNL0), at the output of the gm amplifier that commands a current sense threshold of 0 mV:
(13)
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The critical capacitance limit for this circuit is 6.93 mF, while the actual capacitance of the nine Rubycon capacitors is 9 x 2200 F = 19.8 mF. In this case, the capacitance is safely above the critical value. Multilayer ceramic capacitors are also required for high-frequency decoupling of the processor. The exact number of these MLC capacitors is a function of the board layout space and parasitics. Typical designs use twenty to thirty 10 F MLC capacitors located as close to the processor power pins as is practical.
Feedback Loop Compensation Design for ADOPT
The nearest standard value of COC is 4.7 nF. The resistance of the zero-setting resistor in series with the compensating capacitor is:
RZ = n 3 = = 338 (15) x fOSC x COC x 600 kHz x 4.7 nF
The nearest standard 5% resistor value is 330 . Note that this resistor is only required when COUT approaches CCRIT (within 25% or less). In this example, COUT >> CCRIT, and RZ can therefore be omitted.
Power MOSFETs
Optimized compensation of the ADP3163 allows the best possible containment of the peak-to-peak output voltage deviation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors, and assuming that the capacitance of the output capacitor is larger than the critical value defined by Equation 13, this will produce a peak output voltage deviation equal to the ESR of the output capacitor times the load current change. The optimal implementation of voltage positioning, ADOPT, will create an output impedance of the power converter that is entirely resistive over the widest possible frequency range, including dc, and equal to the maximum acceptable ESR of the output capacitor array. With the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output capacitor bank. With an ideal current-mode-controlled converter, where the average inductor current would respond without delay to the command signal, the resistive output impedance could be achieved by having a single-pole roll-off of the voltage gain of the voltage-error amplifier. The pole frequency must coincide with the ESR zero of the output capacitor bank. The ADP3163 uses constant frequency current-mode control, which is known to have a nonideal, frequency dependent command signal to inductor current transfer function. The frequency dependence manifests in the form of a pair of complex conjugate poles at one-half of the switching frequency. A purely resistive output impedance could be achieved by canceling the complex conjugate poles with zeros at the same complex frequencies and adding a third pole equal to the ESR zero of the output capacitor. Such a compensating network would be quite complicated. Fortunately, in practice it is sufficient to cancel the pair of complex conjugate poles with a single real zero placed at one-half of the switching frequency. Although the end result is not a perfectly resistive output impedance, the remaining frequency dependence causes only a small percentage of deviation from the ideal resistive response. The single-pole and single-zero compensation can be easily implemented by terminating the gm error amplifier with the parallel combination of a resistor (RT) and a series RC network. The value of the terminating resistor RT was determined previously; the capacitance and resistance of the series RC network are calculated as follows:
COC = COUT x ROUT n - = RT x fOSC x RT 19.8 mF x 1.5 m 3 - = 4.4 nF 6.31 k x 600 kHz x 6.31 k
In this example, six N-channel power MOSFETs must be used; three as the main (control) switches, and the remaining three as the synchronous rectifier switches. The main selection parameters for the power MOSFETs are VGS(TH), QG and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3414) dictates whether standard threshold or logic-level threshold MOSFETs must be used. Since VGATE <8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. The maximum output current IO determines the RDS(ON) requirement for the power MOSFETs. When the ADP3163 is operating in continuous mode, the simplifying assumption can be made that in each phase one of the two MOSFETs is always conducting the average inductor current. For VIN = 12 V and VOUT = 1.45 V, the duty ratio of the high-side MOSFET is:
DHSF =
VOUT 1.5 V = = 12.5% VIN 12 V
(16)
The duty ratio of the low-side (synchronous rectifier) MOSFET is: DLSF = 1 - DHSF = 87.5% (17)
The maximum rms current of the high-side MOSFET during normal operation is:
2 IL IO x DHSF x 1 + ( RIPPLE ) = 2 n 3 x IO
I HSF ( MAX ) =
65 A 10.9 A2 x 0.125 x 1 + = 7.7 A 3 3 x 65 A2
(18)
The maximum rms current of the low-side MOSFET during normal operation is:
I LSF ( MAX ) = I HFS ( M AX ) x 7.7 A x 0.875 = 20.4 A 0.125 DLSF = DHSF
(19)
(14)
The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation in the eight MOSFETs of the four-phase converter will be: PFET (TOTAL ) = 0.1 x VMIN x IO = (20) 0.1 x 1.394 V x 65 A = 9.06 W
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Allocating half of the total dissipation for the four high-side MOSFETs and half for the four low-side MOSFETs, and assuming that the resistive and switching losses of the high-side MOSFETs are equal, the required maximum MOSFET resistances will be: RDS (ON )HSF = PFET (TOTAL ) 4 x n x I HSF ( MAX )
2
CIN Selection and Input Current di/dt Reduction
= (21)
In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to VOUT/VIN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by:
I C ( RMS ) = IO x n x DHSF - ( n x DHSF )2 = n
9.06 W = 12.7 m 4 x 3 x 7.7 A2 and: RDS (ON )LSF = PFET (TOTAL ) 2 x n x I LSF ( MAX )
2
65 A x 3 x 0.125 - (3 x 0.125)2 = 10.5 A 3
(25)
= (22)
9.06 W = 3.63 m 2 x 3 x 20.4 A2
Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow higher efficiency, but increase the system cost. A Fairchild FDB7030L (RDS(ON) = 7 m nominal, 10 m worst-case) for the high-side and a Fairchild FDB8030L (RDS(ON) = 3.1 m nominal, 5.6 m worst-case) for the low-side are good choices. The high-side MOSFET dissipation is:
PHSF = RDS (ON )HSF x I HSF ( MAX )
2
Note that the capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 270 F, 16 V OS-CON capacitors with a ripple current rating of 4.4 A each. The ripple voltage across the three paralleled capacitors is: VC ( RIPPLE ) = IO ESRC DHSF x + = n nC nC x CIN x fSW (26)
VIN x I L ( PK ) x QG x fSW + VIN x QRR x fSW = 2 x IG 12 V x 29 A x 35 nC x 200 kHz 10 m x 7.7 A2 + + 2 x1 A +12 V x 150 nC x 200 kHz = 2.17 W
65 A 18 m 0.125 x + = 147 mV 3 3 x 270 F x 200 kHz 3 (23)
Where the first term is the conduction loss of the MOSFET, the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate turn-off current. From the data sheet, for the FDB7030L the value of QG is about 35 nC and the peak gate drive current provided by the ADP3414 is about 1 A. In the third term, QRR, is the charge stored in the body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDB8030L does not give that information, so an estimated value of 150 nC is used. This estimate is based on information found on data sheets of similar devices. In both terms, fSW is the actual switching frequency of the MOSFETs, or 200 kHz. IL(PK) is the peak current in the inductor, or 27 A.) The worst-case low-side MOSFET dissipation is:
2 PLSF = RDS (ON )LSF x I LSF ( MAX ) = 5.6 m x 20.4 A2 = 2.33 W (24)
Multilayer ceramic input capacitors are also required. These capacitors should be placed between the input side of the current sense resistor and the sources of the low side synchronous MOSFETS. These capacitors decouple the high frequency leading edge current spike which supplies the reverse recovery charge of the low side MOSFETS body diode. The exact number required is a function of board layout. Typical designs will use two 10 F MLC capacitors. To reduce the input-current di/dt to below the recommended maximum of 0.1 A/s, an additional small inductor (L > 1 H @ 15 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source.
Note that there are no switching losses in the low-side MOSFET.
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LAYOUT AND COMPONENT PLACEMENT GUIDELINES Power Circuitry
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
9.
1.
For good results, at least a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 12 V), and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the voltage and current sense lines of the ADP3163) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. The power ground plane should not extend under signal components, including the ADP3163 itself. If necessary, follow the preceding guideline to use the signal ground plane as a shield between the power ground plane and the signal circuitry. The GND pin of the ADP3163 should be connected first to the timing capacitor (on the CT pin), and then into the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used. The output capacitors of the power converter should be connected to the signal ground plane even though power current flows in the ground of these capacitors. For this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. Absolutely avoid crossing any signal lines over the switching power path loop, described below.
2.
The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the power MOSFETs, and the power Schottky diode, if used (see next), including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the high current demand with minimal voltage loss.
3.
10. MLC input capacitors should be placed between VIN and power ground as close to the sources of the low-side MOSFETS as possible. 11. To dampen ringing, an RC snubber circuit should be placed from the SW hole of each phase to ground. 12. An optional power Schottky diode (3 A-5 A dc rating) from each lower MOSFET's source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper MOSFETs. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET's body diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. The Schottky diode has to be connected with very short copper traces to the MOSFET to be effective. 13. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air.
4.
5.
6.
7.
8.
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14. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the current sensing resistor, the inductors, the output capacitors, and back to the input capacitors. 15. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These components are: the input capacitors, the power MOSFETs and Schottky diodes, the inductors, the current sense resistor, and any snubbing element that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines.
Signal Circuitry
16. The output voltage is sensed and regulated between the FB pin and the GND pin (which connects to the signal ground plane). The output current is sensed (as a voltage) by the CS+ and CS- pins. In order to avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus the FB trace should be routed atop the signal ground plane and the CS+ and CS- pins. (The CS+ pin should be over the signal ground plane as well.) 17. The CS+ and CS- traces should be Kelvin-connected to the current sense resistor, so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections, does not affect the sensed voltage.
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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
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C02483-1.5-7/01(0)
PRINTED IN U.S.A.

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